1 tm hip2106 100v/1a peak, low cost, high frequency half bridge driver the hip2106 is a high frequency, 100v half bridge n-channel mosfet driver ic, available in 8 lead plastic soic. the low-side and high-side gate drivers are independently controlled and matched to 8ns. this gives the user maximum flexibility in dead-time selection and driver protocol. undervoltage protection on both the low-side and high-side supplies force the outputs low. an on-chip diode eliminates the discrete diode required with other driver ics. a new levelshifter topology yields the low-power benefits of pulsed operation with the safety of dc operation. unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply. pinout hip2106 (soic, pdip) top view features ? drives n-channel mosfet half bridge ? space saving so8 package ? bootstrap supply max voltage to 116v dc ?on-chip 1 ? bootstrap diode ? fast propagation times needed for multi-mhz circuits ? drives 1000pf load at 500khz with rise and fall times of typically 20ns ? cmos input thresholds for improved noise immunity ? independent inputs for non-half bridge topologies ? no start-up problems ? outputs unaffected by supply glitches, hs ringing below ground, or hs slewing at high dv/dt ? low power consumption ? wide supply range ? supply undervoltage protection ?3 ? output resistance applications ? telecom half bridge power supplies ? avionic dc-dc converters ? two-switch forward converters ? active clamp forward converters application block diagram ordering information part number temp. range ( o c) package pkg. no. hip2106ib -40 to 85 8 ld soic m8.15 hip2106ip -40 to 85 8 ld pdip e8.3 5 6 8 7 4 3 2 1 v dd hb ho hs lo li hi v ss secondary circuit +100v control controller pwm li hi ho lo v dd hs hb +12v v ss hip2106 reference and isolation drive lo drive hi data sheet august 1999 fn4406.2 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 321-724-7143 | intersil (and design) is a trademark of intersil americas inc. copyright ? intersil americas inc. 2002. all rights reserved
2 functional block diagram other applications figure 1. two-switch forward converter figure 2. forward converter with an active clamp under voltage v dd hi li v ss 1 5 6 7 driver driver 2 3 4 hb ho hs 8 lo level shift under voltage secondary hip 2106 isolation pwm +48v +12v circuit secondary circuit hip 2106 isolation pwm +48v +12v hip2106
3 absolute maximum ratings thermal information supply voltage, v dd, v hb -v hs . . . . . . . . . . . . . . . . . . . -0.3v to 18v li and hi voltages . . . . . . . . . . . . . . . . . . . . . . . . .-3v to v dd +0.3v voltage on lo . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd +0.3v voltage on ho . . . . . . . . . . . . . . . . . . . . . . v hs -0.3v to v hb +0.3v voltage on hs (continuous) . . . . . . . . . . . . . . . . . . . . . -1v to 110v voltage on hb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+118v average current in v dd to hb diode . . . . . . . . . . . . . . . . . . 100ma esd classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . class 1 (1kv) thermal resistance (typical, note 1) ja ( o c/w) soic package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 pdip package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 hs slew rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10v/ns maximum power dissipation at 25 o c in free air . . . . . . . . .780mw maximum storage temperature range . . . . . . . . . -65 o c to 150 o c maximum junction temperature range . . . . . . . . . -55 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (lead tips only) recommended operating conditions supply voltage, v dd . . . . . . . . . . . . . . . . . . . . . . . . . +9v to +16.5v voltage on hs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -1v to 100v voltage on hs . . . . . . . . . . . . . . .(repetitive transient) -5v to 105v voltage on hb . . v hs +8v to v hs +16.5v and v dd -1v to v dd +100v caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ja is measured with the component mounted on an evaluation pc board in free air. 2. all voltages relative to pin 4, v ss unless otherwise specified. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameter symbol test conditions t j = 25 o c t j = -40 o c to 125 o c units min typ max min max supply currents v dd quiescent current i dd li = hi = 0v - 0.1 0.15 - 0.2 ma v dd operating current i ddo f = 500khz - 1.5 2.5 - 3 ma total hb quiescent current i hb li = hi = 0v - 0.1 0.15 - 0.2 ma total hb operating current i hbo f = 500khz - 1.5 2.5 - 3 ma hb to v ss current, quiescent i hbs v hs = v hb = 116.5v - 0.05 1 - 10 a hb to v ss current, operating i hbso f = 500khz - 0.7 - - - ma input pins low level input voltage threshold v il 45.4 - 3 - v high level input voltage threshold v ih -5.88 - 9 v input voltage hysteresis v ihys -0.4---v input pulldown resistance r i -200-100500k ? under voltage protection v dd rising threshold v ddr 77.386.58.5 v v dd threshold hysteresis v ddh -0.5---v hb rising threshold v hbr 6.5 6.9 7.5 6 8 v hb threshold hysteresis v hbh -0.4---v boot strap diode low-current forward voltage v dl i vdd-hb = 100 a - 0.45 0.55 - 0.7 v high-current forward voltage v dh i vdd-hb = 100ma - 0.7 0.8 - 1 v dynamic resistance r d i vdd-hb = 100ma - 0.8 1 - 1.5 ? lo gate driver low level output voltage v oll i lo = 100ma - 0.25 0.3 - 0.4 v high level output voltage v ohl i lo = -100ma, v ohl = v dd -v lo - 0.25 0.3 - 0.4 v peak pullup current i ohl v lo = 0v -1---a peak pulldown current i oll v lo = 12v -1---a ho gate driver low level output voltage v olh i ho = 100ma - 0.25 0.3 - 0.4 v high level output voltage v ohh i ho = -100ma, v ohh = v hb -v ho - 0.25 0.3 - 0.4 v peak pullup current i ohh v ho = 0v -1---a hip2106
4 peak pulldown current i olh v ho = 12v -1---a switching specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified parameter symbol test conditions t j = 25 o c t j = - 40 o c to 125 o c units min typ max min max lower turn-off propagation delay (li falling to lo falling) t lphl -4070-90ns upper turn-off propagation delay (hi falling to ho falling) t hphl -4070-90ns lower turn-on propagation delay (li rising to lo rising) t lplh -4070-90ns upper turn-on propagation delay (hi rising to ho rising) t hplh -4070-90ns delay matching: lower turn-on and upper turn-off t mon -416-20ns delay matching: lower turn-off and upper turn-on t moff -416-20ns either output rise/fall time t rc , t fc c l = 1000pf - 20 - - - ns either output rise/fall time (3v to 9v) t r , t f c l = 0.1 f - 1.0 1.2 - 1.6 us either output rise time driving dmos t rd c l = irfr120 - 40 - - - ns either output fall time driving dmos t fd c l = irfr120 - 20 - - - ns minimum input pulse width that changes the output t pw ----100ns bootstrap diode turn-on or turn-off time t bs -20---ns pin descriptions pin number symbol description 1v dd positive supply to lower gate drivers. de-couple this pin to v ss (pin 7). bootstrap diode connected to hb (pin 2). 2 hb high-side bootstrap supply. external bootstrap capacitor is required. connect positive side of bootstrap capacitor to this pin. bootstrap diode is on-chip. 3 ho high-side output. connect to gate of high-side power mosfet. 4 hs high-side source connection. connect to source of high-side power mosfet. connect negative side of bootstrap capacitor to this pin. 5 hi high-side input. 6 li low-side input. 7v ss chip negative supply, generally will be ground. 8 lo low-side output. connect to gate of low-side power mosfet. timing diagrams figure 3. figure 4. electrical specifications v dd = v hb = 12v, v ss = v hs = 0v, no load on lo or ho, unless otherwise specified (continued) parameter symbol test conditions t j = 25 o c t j = -40 o c to 125 o c units min typ max min max t hplh , t lplh t hphl , t lphl hi, li ho, lo t mon t moff li hi lo ho hip2106
5 typical performance curves figure 5. operating current vs frequency figure 6. level shifter current vs frequency figure 7. high level output voltage vs temperature figure 8. low level output voltage vs temperature figure 9. undervoltage lockout threshold vs temperature figure 10. undervoltage lockout hysteresis vs temperature t = 125 o c t = 25 o c t = -40 o c t = 150 o c 10 100 500 10 1 0.1 0.01 frequency (khz) i ddo , i hbo (ma) 50 t = 150 o c 10 1 0.1 0.01 i hbso (ma) 10 100 1000 frequency (khz) t = 25 o c t = 125 o c t = -40 o c temperature ( o c) v ohl , v ohh (mv) 500 400 300 200 100 -50 0 50 100 150 v hb = v dd = 9v v hb = v dd = 12v v hb = v dd = 14v v hb = v dd = 16.5v temperature ( o c) v oll , v olh (mv) 500 400 300 200 100 -50 0 50 100 150 v hb = v dd = 9v v hb = v dd = 12v v hb = v dd = 14v v hb = v dd = 16.5v temperature ( o c) -50 0 50 100 150 7.6 7.4 7.2 7.0 6.8 6.6 v ddr v hbr v hbr , v ddr (mv) temperature ( o c) -50 0 50 100 150 0.54 0.5 0.46 0.42 0.38 0.3 v ddh v hbh v hbh , v ddh (mv) 0.34 hip2106
6 figure 11. propagation delays vs temperature figure 12. pullup current vs output voltage figure 13. pulldown current vs output voltage figure 14. bootstrap diode i-v characteristics figure 15. bias current vs voltage typical performance curves (continued) t hphl t hplh t lphl t lplh temperature ( o c) -50 0 50 100 150 60 50 40 30 t lplh , t lphl , t hplh , t hphl (ns) 6 2.0 i ho , i lo (a) 12 10 8 4 2 0 2.5 1.5 1.0 0.5 0 v ho , v lo (v) 6 2.0 i lo , i ho (a) 12 10 8 4 2 0 2.5 1.5 1.0 0.5 0 v lo , v ho (v) 0.8 1 0.1 0.01 0.001 1 ? 10 -4 1 ? 10 -5 1 ? 10 -6 0.7 0.6 0.5 0.4 0.3 forward voltage (v) forward current (a) v dd , v hb (v) 0 5 10 15 60 50 40 0 i dd , i hb ( a) 30 20 10 i dd vs v dd i hb vs v hb hip2106
7 hip2106 dual-in-line plastic packages (pdip) c l e e a c e b e c -b- e1 index 12 3 n/2 n area seating base plane plane -c- d1 b1 b e d d1 a a2 l a 1 -a- 0.010 (0.25) c a m bs notes: 1. controlling dimensions: inch. in case of conflict between english and metric dimensions, the inch dimensions control. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. symbols are defined in the ?mo series symbol list? in section 2.2 of publication no. 95. 4. dimensions a, a1 and l are measured with the package seated in jedec seating plane gauge gs - 3. 5. d, d1, and e1 dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. e and are measured with the leads constrained to be perpendicular to datum . 7. e b and e c are measured at the lead tips with the leads unconstrained. e c must be zero or greater. 8. b1 maximum dimensions do not include dambar protrusions. dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. n is the maximum number of terminal positions. 10. corner leads (1, n, n/2 and n/2 + 1) for e8.3, e16.3, e18.3, e28.3, e42.6 will have a b1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). e a -c- e8.3 (jedec ms-001-ba issue d) 8 lead dual-in-line plastic package symbol inches millimeters notes minmaxminmax a - 0.210 - 5.33 4 a1 0.015 - 0.39 - 4 a2 0.115 0.195 2.93 4.95 - b 0.014 0.022 0.356 0.558 - b1 0.045 0.070 1.15 1.77 8, 10 c 0.008 0.014 0.204 0.355 - d 0.355 0.400 9.01 10.16 5 d1 0.005 - 0.13 - 5 e 0.300 0.325 7.62 8.25 6 e1 0.240 0.280 6.10 7.11 5 e 0.100 bsc 2.54 bsc - e a 0.300 bsc 7.62 bsc 6 e b - 0.430 - 10.92 7 l 0.115 0.150 2.93 3.81 4 n8 89 rev. 0 12/93
8 all intersil u.s. products are manufactured, assembled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications can be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com sales office headquarters north america intersil corporation 7585 irvine center drive suite 100 irvine, ca 92618 tel: (949) 341-7000 fax: (949) 341-7123 intersil corporation 2401 palm bay rd. palm bay, fl 32905 tel: (321) 724-7000 fax: (321) 724-7946 europe intersil europe sarl ave. william graisse, 3 1006 lausanne switzerland tel: +41 21 6140560 fax: +41 21 6140579 asia intersil corporation unit 1804 18/f guangdong water building 83 austin road tst, kowloon hong kong tel: +852 2723 6339 fax: +852 2730 1433 hip2106 small outline plastic packages (soic) index area e d n 123 -b- 0.25(0.010) c a m bs e -a- l b m -c- a1 a seating plane 0.10(0.004) h x 45 o c h 0.25(0.010) b m m notes: 1. symbols are defined in the ?mo series symbol list? in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension ?d? does not include mold flash, protrusions or gate burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e? does not include interlead flash or protrusions. interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. the lead width ?b?, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. controlling dimension: millimeter. converted inch dimensions are not necessarily exact. m8.15 (jedec ms-012-aa issue c) 8 lead narrow body small outline plastic package symbol inches millimeters notes min max min max a 0.0532 0.0688 1.35 1.75 - a1 0.0040 0.0098 0.10 0.25 - b 0.013 0.020 0.33 0.51 9 c 0.0075 0.0098 0.19 0.25 - d 0.1890 0.1968 4.80 5.00 3 e 0.1497 0.1574 3.80 4.00 4 e 0.050 bsc 1.27 bsc - h 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 l 0.016 0.050 0.40 1.27 6 n8 87 0 o 8 o 0 o 8 o - rev. 0 12/93
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